Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). 1. Instruction fetch. 2. Instruction decode and register fetch. 3. Execute. 4. Memory Access. 5. Registers Write back.
![[ Example OF PIPELINE ]](fivestagepipeline.gif){kind=small}
![[ RISC ARCHITECTURE PIPELINE EXAMPLE ]](5stage.gif)
