First Draft

The Fetch and Execute Cycles

In order to explain the Fetch/Decode/Execution cycle we will assume the following:

Given the Von-Newman CPU structure we will consider four categories of instructions plus two "jump" cases (conditional and unconditional)
For the following examples, memory is word addressable
The instruction execution is effectuated in two phases

Fetch/Decode Phase - where the operation code address is fetched (read) from memory. The actions to be executed are identified, and (if the case) the address(es) of the memory operand(s) are loaded.
Execution - where the actions (operations) specified by the instructions are effectively executed

A computer program basically constitutes of instructions. We are, today, generally used to program computers using High Level Languages (HLL - C⁺⁺, C, Pascal, Fortran, Java, etc.).

Those programming languages are not understood by the CPU, so the compiler compiles our code into something that the machine will be able to handle or execute. The output of this phase is a machine language program.

But the translations are not quite over.

The computer is not able to handle or to understand these lines of code either, so here is where the fetch-execute phase takes place. The CPU is only able to understand binary code and the machine language was designed in a way that all of the instruct ions, that we can possibly make use of, are already translated into binary code and kept into a table in a specified area of the memory.

What happens when I make use of a assembly language instruction?

As we'll see in the examples, there are basically four categories of instructions:

No address instruction
Two addresses instruction
Four addresses instruction
Four addresses instruction

The so-called OP (operation code) is the binary code associated with the particular instruction (add, sub, etc). This is what we are looking for, this is finally something that could be used by the CPU.

It is just after the fetch phase that this OP will be available and the instruction could be executed. Instructions are loaded into memory sequentially and the PC (Program Counter) is the register that keeps tracks of the execution point in the program . The PC contains an address in memory and once the content of this register is read the content of the address is read from memory into the IR (Instruction Register).

Unfortunately there is not direct correspondence between the content of the PC and what I want to put in the IR because the PC contains an address into a table in the memory where the OP is contained. So in order to load the real OP into the IR the OP has to be retrieved from memory. These two steps are know as decode phase and they are necessary for the correct execution of the instruction. At this point the PC is incremented in order to point to the next instruction of the program.

The content of the above paragraph is what is known as fetch phase.

At this point the instruction is executed using the necessary resources (ALU, registers, etc.) and the result are stored in those locations specified by the OP.

In the case when we need to use instructions which refers or specify to a specific memory location, those addresses has to be loaded before the execution phase begins so that the CPU knows where to retrieve or store operators needed in the instruction.

Examples

No address instructions

INC R0 # increment by 1 the value from register R0 # instruction represented on one word

Initially, PC (program counter register) contains the address of the current instruction to

be executed.

The sequence that executes the above instruction:

MAR ç PC # the address of the instruction is in MAR

MDR ç mem(MAR) # read the instruction code from memory

PC ç PC +1 # the address of the next instruction

IR ç MDR # instruction code in instruction register

R0 ç R0 +1 # increment the content of register R0

2. One address instructions

ADDX, R0 # X=X+R0

# instruction represented on two words, first word is the operation code, the second is the address of the memory operand X

The sequence that executes the above instruction:

MAR ç PC # the address of the instruction is in

MDR ç mem(MAR) # read the instruction code from memory

PC ç PC +2 # the address of the next instruction in this case the

instruction takes two words

IR ç MDR # instruction code in instruction register

MAR ç MAR +l # the address of the memory operand is MAR

MDR ç mem(MAR) # the value of the memory operand in MDR

R ç MDR # value of operand in working register R

R ç R + RO # perform addition

MDR ç R # sum in MDR

mem(MAR) ç MDR # store the result in memory ( address of destination

# is address of operand X)

3. Two address instructions

ADD X, Y #X=X+Y

# instruction represented on three words, first word is the operation code, the second is the address of the memory operand Y and the third id the address of memory operand X.

The sequence that executes the above instruction:

MAR ç PC # the address of the instruction is in MAR

MDR ç mem(MAR) # read the instruction code from memory

PC ç PC +3 # the address of the next instruction

IR ç MDR # instruction code in instruction register in this

case the instruction takes 3 words

MAR ç MAR + 1 # the address of the memory operand Y is MAR

MDR ç mem(MAR) # the value of the memory operand Y in MDR

T ç MDR # value of operand Y in temporary register T

MAR ç MAR +1 # the address of the memory operand X is MAR

MDR ç mem(MAR) # the value of the memory operand X in MDR

R ç MDR # value of operand X in working register R

R ç R+T # perform addition

MDR ç R # sum in MDR

mem(MAR) ç MDR # store the result in memory ( address of destination

is address of operand X)

4. Three addresses instructions

ADD X, Y,Z # Z=X+Y

# instruction represented on four words. first word is the operation code, the second is the address of the memory operand Y and the third is the address of memory operand X and fourth word is the address of operand Z.

A sequence very similar to the "two address instruction" will be adopted for this type of instruction except there is an additional fetch/decode for the additional address.

5. Execution of the conditional jump instruction

JMP alpha # jump to instruction from address alpha

# instruction represented on two words, first word is the operation code, the second is the address of the variable alpha, that contains the address where to jump, in the code section. Jump instruction affect the current flow of execution: no longer th e instruction from the next address will be executed, but the instruction allocated at other address from the code section.

The sequence that executes the above instruction:

MAR ç PC # the address of the instruction is in MAR

MDR ç mem(MAR) # read the instruction code from memory

PC ç PC +2 # the address of the next (physical) instruction

IR ç MDR # instruction code in instruction register

MAR ç MAR + 1 # the address of alpha in MAR

MDR ç mem(MAR) # the value of the jump address is in MDR

PC ç MDR # the address of the next instruction to be executed

6. Execution of conditional jump instruction

Pseudocode:

if cond goto alpha; where cond is a boolean expression

if cond is true then the instruction from the address alpha is executed.

JMP- cond, alpha # conditional jump to instruction from address alpha

# instruction represented on two words, first word is the operation code including the condition, the second is the address of the variable alpha, that contains the address where to jump, in the code section.

The sequence that executes the above instruction:

MAR ç PC # the address of the instruction is in MAR

MDR ç mem(MAR) # read the instruction code from memory

PC ç PC +2 # the address of the next (physical) instruction

IR ç MDR # instruction code in instruction register

# if the IR(cond) is true then

MAR ç MAR +1 # the address of alpha in MAR

MDR ç mem(MAR) # the value of the jump address is in MDR

PC ç MDR # the address of the next instruction to be executed

# end if