CS546 Parallel Processing

Instructor: Xian-He Sun

Homework 3 (Due date: Feb. 23, 2010, Tuesday)

• • How does cache associativity affect the cache performance?
  • Just providing deeper memory hierarchies does NOT bridge the gap between processor and memory performance. Why?
• Derive the formula for calculating the average access time for a word in a system with three levels of cache. Assume the following values for a theoretical system containing an L1, L2, and L3 cache.

  Location                 Latency
  ---------                -------------
  L1                       5 ns
  L2                       10 ns
  L3                       35 ns
  Main Memory              100 ns
  

  If an application has following hit rates, what is the average memory access time for a memory word?

  Location                 Hit rate
  ------------             ----------
  L1                       45%
  L2                       75%
  L3                       90%
  Main Memory              100%
  

• What is the purpose of benchmark and benchmarking? What are the merits of a good benchmark?
• If you need to evaluate a parallel machine for scientific computing, which existing benchmark should you use and why?
• Exercise 4.7 (Text: Grama, et al, Addison Wesley)
• Exercise 4.11 (Text: Grama, et al, Addison Wesley)
• Exercise 4.14 (Text: Grama, et al, Addison Wesley)
• Exercise 6.4 (Text: Grama, et al, Addison Wesley)
• Read Chapter 4 and 6 of the text book.

Contact Information

• Email: sun at iit dot edu
• Telephone: (312) 567-5260
• FAX: (312) 567-5067
• USMail: Xian-He Sun Department of Computer Science Illinois Institute of Technology 10 West 31st Street Chicago, IL 60616-3793